library ieee;
use ieee.std_logic_1164.all;

entity controller is
    port(
    Op, Funct: in std_logic_vector(5 downto 0);
    MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump: out std_logic;
    AluControl: out std_logic_vector(2 downto 0)
    );
end controller;

architecture behav of controller is
    component maindec
    port(
    Op: in std_logic_vector(5 downto 0);
    MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump: out std_logic;
    AluOp: out std_logic_vector(1 downto 0)
    );
    end component;

    component aludec
    port(
    AluOp: in std_logic_vector(1 downto 0);
    Funct: in std_logic_vector(5 downto 0);
    AluControl: out std_logic_vector(2 downto 0)
    );
    end component;

    signal AO_s: std_logic_vector(1 downto 0);

begin
    MDec: maindec port map(Op, MemToReg, MemWrite, Branch, AluSrc, RegDst,
          RegWrite, Jump, AO_s);
    ADec: aludec port map(AO_s, Funct, AluControl);
end behav;
